CC2510F16 Datasheet, PDF (20/244 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller

CC2510Fx / CC2511Fx
6.10 7 - 12 bit ADC
T_A = 25°C, VDD = 3.0V if nothing else stated. The numbers given here are based on tests performed
in accordance with IEEE Std 1241-2000 [7]. The ADC data are from CC2430 characterization. As the
CC2510x/C2511Fx uses the same ADC, the numbers listed in Table 18 should be good indicators of the
performance to be expected from CC2510x and CC2511x. Note that these numbers will apply for 24 MHz
operated systems (like CC2510x using a 24 MHz crystal or CC2511x using a 48 MHz crystal).
Performance will be slightly different for other crystal frequencies (e.g. 26 MHz and 27 MHz).
Parameter
Min Typ Max Unit Condition/Note
Input voltage
0
VDD V VDD is the voltage on the AVDD pin (2.0 - 3.6 V)
External reference
0
voltage
VDD V VDD is the voltage on the AVDD pin (2.0 - 3.6 V)
External reference
0
voltage differential
VDD V VDD is the voltage on the AVDD pin (2.0 - 3.6 V)
Input resistance, signal
Full-Scale Signal⁵
ENOB⁵
197
kΩ Simulated using 4 MHz clock speed (see Section 12.10.2.7)
2.97
V Peak-to-peak, defines 0 dBFS
5.7
bits 7-bits setting
Single ended input
7.5
9-bits setting
9.3
10-bits setting
ENOB⁵
10.8
12-bits setting
6.5
bits 7-bits setting
Differential input
8.3
9-bits setting
10.0
10-bits setting
11.5
12-bits setting
Useful Power Bandwidth
THD⁵
0 - 20
kHz 7-bits setting, both single and differential
-Single ended input
−75.2
dB 12-bits setting, −6 dBFS
-Differential input
−86.6
12-bits setting, −6 dBFS
Signal To Non-Harmonic
Ratio⁵
-Single ended input
70.2
dB 12-bits setting
-Differential input
79.3
12-bits setting
Spurious Free Dynamic
Range⁵
-Single ended input
78.8
dB 12-bits setting, −6 dBFS
-Differential input
88.9
12-bits setting, −6 dBFS
CMRR, differential input
<−84
dB 12- bit setting, 1 kHz Sine (0 dBFS), limited by ADC resolution
Crosstalk, single ended
input
<−84
dB 12- bit setting, 1 kHz Sine (0 dBFS), limited by ADC resolution
Offset
−3
mV Mid. Scale
Gain error
DNL⁵
0.68
%
0.05
LSB 12-bits setting, mean
0.9
12-bits setting, max
INL⁵
4.6
LSB 12-bits setting, mean
13.3
12-bits setting, max
5 _{Measured with 300 Hz Sine input and VDD as reference}
SWRS055F
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