CC2510F16 Datasheet, PDF (180/244 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller

CC2510Fx / CC2511Fx
0xDE11: USBCSIL - IN EP{1 - 5} Control and Status Low
Bit Field Name
Reset R/W Description
7
-
6 CLR_DATA_TOG
0
5 SENT_STALL
0
4 SEND_STALL
0
3 FLUSH_PACKET
0
2 UNDERRUN
0
1 PKT_PRESENT
0
0 INPKT_RDY
0
R0 Not used
R/W Setting this bit will reset the data toggle to 0. Thus, setting this bit will force
H0 the next data packet to be a DATA0 packet. This bit is automatically
cleared.
R/W This bit is set when a STALL handshake has been sent. The FIFO will be
flushed and the INPKT_RDY bit in this register will be de-asserted. An
interrupt request (IN EP{1 - 5}) will be generated if the interrupt is enabled.
This bit must be cleared from firmware.
R/W Set this bit to 1 to make the USB controller reply with a STALL handshake
when receiving IN tokens. Firmware must clear this bit to end the STALL
condition. It is not possible to stall an isochronous endpoint, thus this bit will
only have effect if the IN endpoint is configured as bulk/interrupt.
R/W Set to 1 to flush next packet that is ready to transfer from the IIN FIFO. The
H0 INPKT_RDY bit in this register will be cleared. If there are two packets in
the IN FIFO due to double buffering, this bit must be set twice to completely
flush the IN FIFO. This bit is automatically cleared.
R/W In isochronous mode, this bit is set if an IN token is received when
INPKT_RDY=0, and a zero length data packet is transmitted in response to
the IN token. In Bulk/Interrupt mode, this bit is set when a NAK is returned
in response to an IN token. Firmware should clear this bit.
R
This bit is 1 when there is at least one packet in the IN FIFO.
R/W Set this bit when a data packet has been loaded into the IN FIFO to notify
H0 the USB controller that a new data packet is ready to be transferred. When
the data packet has been sent, this bit is cleared and an interrupt request
(IN EP{1 - 5}) will be generated if the interrupt is enabled.
0xDE12: USBCSIH - IN EP{1 - 5} Control and Status High
Bit Field Name
Reset R/W Description
7 AUTOSET
0
6 ISO
0
5:4
10
3 FORCE_DATA_TOG 0
2:1
-
0 IN_DBL_BUF
0
R/W When this bit is 1, the USBCSIL.INPKT_RDY bit is automatically asserted
when a data packet of maximum size (specified by USBMAXI) has been
loaded into the IN FIFO.
R/W Selects IN endpoint type
0 Bulk/Interrupt
1 Isochronous
R/W Reserved. Always write 10
R/W Setting this bit will force the IN endpoint data toggle to switch and the data
packet to be flushed from the IN FIFO even though an ACK was received.
This feature can be useful when reporting rate feedback for isochronous
endpoints.
R0 Not used
R/W Double buffering enable (IN FIFO)
0 Double buffering disabled
1 Double buffering enabled
0xDE13: USBMAXO - Max. Packet Size for OUT{1 - 5} Endpoint
Bit Field Name
Reset R/W Description
7:0 USBMAXO[7:0]
0x00
R/W Maximum packet size in units of 8 bytes for OUT endpoint selected by
USBINDEX register. The value of this register should correspond to the
wMaxPacketSize field in the Standard Endpoint Descriptor for the endpoint.
This register must not be set to a value grater than the available FIFO
memory for the endpoint.
SWRS055F
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