CC2510F16 Datasheet, PDF (173/244 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller

The following events may generate an OUT
EPx interrupt request:
• A data packet has been received
(USBCSOL.OUTPKT_RDY=1)
• A STALL has been sent
(USBCSIL.SENT_STALL=1).
Only
Bulk/Interrupt endpoints can be stalled
Any of these events will cause
USBOIF.OUTEPxIF to be asserted
regardless of the status of the OUT EPx
interrupt mask bit USBOIE.OUTEPxIE. If the
OUT EPx interrupt mask bit is set to 1, the
CPU interrupt flag IRCON2.USBIF will also be
asserted. An interrupt request is only
generated
if
IEN2.USBIE
and
USBOIE.OUTEPxIE are both set to 1.
12.16.6.5 Bulk/Interrupt IN Endpoint
Interrupt IN transfers occur at regular intervals
while bulk IN transfers utilize available
bandwidth not allocated to isochronous,
interrupt, or control transfers.
Interrupt IN endpoints may set the
USBCSIH.FORCE_DATA_TOG bit. When this bit
is set the data toggle bit is continuously
toggled regardless of whether an ACK was
received or not. This feature is typically used
by interrupt IN endpoints that are used to
communicate rate feedback for Isochronous
endpoints.
A Bulk/Interrupt IN endpoint can be stalled by
setting the USBCSIL.SEND_STALL bit to 1.
When the endpoint is stalled, the USB
controller will respond with a STALL
handshake to IN tokens. The
USBCSIL.SENT_STALL bit will then be set
and an interrupt will be generated, if enabled.
A bulk transfer longer than the maximum
packet size is performed by splitting the
transfer into a number of data packets of
maximum size followed by a smaller data
packet containing the remaining bytes. If the
transfer length is a multiple of the maximum
packet size, a zero length data packet is sent
last. This means that a packet with a size less
than the maximum packet size denotes the
end of the transfer. The AutoSet feature can
be useful in this case, since many data
packets will be of maximum size.
12.16.6.6 Isochronous IN Endpoint
An Isochronous IN endpoint is used to transfer
periodic data from the USB controller to the
host (one data packet every USB frame).
CC2510Fx / CC2511Fx
If there is no data packet loaded in the IN FIFO
when the USB host requests data, the USB
controller sends a zero length data packet and
the USBCSIL.UNDERRUN bit will be asserted.
Double buffering requires that a data packet is
loaded into the IN FIFO during the frame
preceding the frame where it should be sent. If
the first data packet is loaded before an IN
token is received, the data packet will be sent
during the same frame as it was loaded and
hence violate the double buffering strategy.
Thus, when double buffering is used, the
USBPOW.ISO_WAIT_SOF bit should be set to
1 to avoid this. Setting this bit will ensure that a
loaded data packet is not sent until the next
SOF token has been received.
The AutoSet feature will typically not be used
for isochronous endpoints since the packet
size will increase or decrease from frame to
frame.
12.16.6.7 Bulk/Interrupt OUT Endpoint
Interrupt OUT transfers occur at regular
intervals while bulk OUT transfers utilize
available bandwidth not allocated to
isochronous, interrupt, or control transfers.
A Bulk/Interrupt OUT endpoint can be stalled
by setting the USBCSOL.SEND_STALL bit to
1. When the endpoint is stalled, the USB
controller will respond with a STALL
handshake when the host is done sending the
data packet. The data packet is discarded and
is not placed in the OUT FIFO. The USB
controller
will
assert
the
USBCSOL.SENT_STALL bit when the STALL
handshake is sent and generate an interrupt
request if the OUT endpoint interrupt is
enabled.
As the AutoSet feature is useful for bulk IN
endpoints, the AutoClear feature is useful for
OUT endpoints since many packets will be of
maximum size.
12.16.6.8 Isochronous OUT Endpoint
An Isochronous OUT endpoint is used to
transfer periodic data from the host to the USB
controller (one data packet every USB frame).
If there is no buffer available when a data
packet is being received, the
USBCSOL.OVERRUN bit will be asserted and
the packet data will be lost. Firmware can
reduce the chance for this to happen by using
double buffering and use DMA to effectively
unload data packets.
SWRS055F
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