CC2510F16 Datasheet, PDF (153/244 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller

The interrupt enables and flags are
summarized below.
Interrupt enable bits:
• USART0 RX : IEN0.URX0IE
• USART1 RX : IEN0.URX1IE
• USART0 TX : IEN2.UTX0IE
• USART1 TX : IEN2.UTX1IE
Interrupt flags:
• USART0 RX : TCON.URX0IF
• USART1 RX : TCON.URX1IF
• USART0 TX : IRCON2.UTX0IF
• USART1 TX : IRCON2.UTX1IF
12.14.6 USART DMA Triggers
There are two DMA triggers associated with
each USART (URX0, UTX0, URX1, and
UTX1). The DMA triggers are activated by RX
complete and TX complete events i.e. the
same events that might generate USART
interrupt requests. A DMA channel can be
configured using a USART Receive/transmit
CC2510Fx / CC2511Fx
buffer, UxDBUF, as source or destination
address.
Note: For systems requiring setting
UxGCR.CPHA=1, the DMA can not be
used.
Refer to Table 51 on Page 104 for an overview
of the DMA triggers.
12.14.7 USART Registers
The registers for the USART are described in
this section. For each USART there are five
registers consisting of the following (x refers to
USART number i.e. 0 or 1):
• UxCSR USART x Control and Status
• UxUCR USART x UART Control
• UxGCR USART x Generic Control
• UxDBUF USART x Receive/Transmit
Data Buffer
• UxBAUD USART x Baud Rate Control
SWRS055F
Page 153 of 241