CC2510F16 Datasheet, PDF (181/244 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller

CC2510Fx / CC2511Fx
0xDE14: USBCSOL - OUT EP{1 - 5} Control and Status Low
Bit Field Name
Reset
R/W Description
7
CLR_DATA_TOG 0
6
SENT_STALL
0
5
SEND_STALL
0
4
FLUSH_PACKET 0
3
DATA_ERROR
0
2
OVERRUN
0
1
FIFO_FULL
0
0
OUTPKT_RDY
0
R/W Setting this bit will reset the data toggle to 0. Thus, setting this bit will force
H0 the next data packet to be a DATA0 packet. This bit is automatically
cleared.
R/W This bit is set when a STALL handshake has been sent. An interrupt
request (OUT EP{1 - 5}) will be generated if the interrupt is enabled. This
bit must be cleared from firmware
R/W Set this bit to 1 to make the USB controller reply with a STALL handshake
when receiving OUT tokens. Firmware must clear this bit to end the STALL
condition. It is not possible to stall an isochronous endpoint, thus this bit will
only have effect if the IN endpoint is configured as bulk/interrupt.
R/W Set to 1 to flush next packet that is to be read from the OUT FIFO. The
H0 OUTPKT_RDY bit in this register will be cleared. If there are two packets in
the OUT FIFO due to double buffering, this bit must be set twice to
completely flush the OUT FIFO. This bit is automatically cleared.
R
This bit is set if there is a CRC or bit-stuff error in the packet received.
Cleared when OUTPKT_RDY is cleared. This bit will only be valid if the
OUT endpoint is isochronous.
R/W This bit is set when an OUT packet cannot be loaded into the OUT FIFO.
Firmware should clear this bit. This bit is only valid in isochronous mode
R
This bit is asserted when no more packets can be loaded into the OUT
FIFO full.
R/W This bit is set when a packet has been received and is ready to be read
from OUT FIFO. An interrupt request (OUT EP{1 - 5}) will be generated if
the interrupt is enabled. This bit should be cleared when the packet has
been unloaded from the FIFO.
0xDE15: USBCSOH - OUT EP{1 - 5} Control and Status High
Bit Field Name
Reset
R/W Description
7
AUTOCLEAR
0
6
ISO
0
5:4
00
3:1
-
0
OUT_DBL_BUF
0
R/W When this bit is set to 1, the USBCSOL.OUTPKT_RDY bit is automatically
cleared when a data packet of maximum size (specified by USBMAXO) has
been unloaded to the OUT FIFO.
R/W Selects OUT endpoint type
0 Bulk/Interrupt
1 Isochronous
R/W Reserved. Always write 00
R0 Not used
R/W Double buffering enable (OUT FIFO)
0 Double buffering disabled
1 Double buffering enabled
0xDE16: USBCNT0 - Number of Received Bytes in EP0 FIFO (USBINDEX=0)
Bit Field Name
7:6
5:0 USBCNT0[5:0]
Reset
-
000000
R/W Description
R0 Not used
R
Number of received bytes into EP 0 FIFO. Only valid when OUTPKT_RDY
is asserted
0xDE16: USBCNTL - Number of Bytes in EP{1 – 5} OUT FIFO Low
Bit Field Name
Reset
R/W Description
7:0 USBCNT[7:0]
0x00
R
8 LSB of number of received bytes into OUT FIFO selected by USBINDEX
register. Only valid when USBCSOL.OUTPKT_RDY is asserted.
SWRS055F
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