CC2510F16 Datasheet, PDF (106/244 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller

CC2510Fx / CC2511Fx
Byte Bit
Offset
7
3
7
2
7
1:0
Field Name
Description
IRQMASK
M8
PRIORITY[1:0]
Interrupt Mask for this channel.
0 Disable interrupt generation
1 Enable interrupt generation upon reaching transfer count
When variable length transfer count is used (VLEN≠000 and VLEN≠111) this field
determines whether to use seven or eight bits of the first byte in source data to
determine the transfer count. Only applicable when WORDSIZE=0.
0 Use all 8 bits
1 Use 7 LSB
The DMA channel priority:
00 Low, DMA access will always defer to a CPU access
01 Normal, guarantees that DMA access prevails over CPU on at least every
second try.
10 High, DMA access will always prevail over CPU access.
11 Reserved
Table 52: DMA Configuration Data Structure
12.5.8 DMA Registers
This section describes the SFRs associated
with the DMA Controller.
DMAARM (0xD6) - DMA Channel Arm
Bit Field Name Reset R/W Description
7
ABORT
0
R0/W
DMA abort. Ongoing byte/word transfers or armed DMA channels will be aborted
when writing a 1 to this bit, and at the same time select which DMA channels to
abort by setting the corresponding, DMAARM.DMAARMn bits to 1
0 Normal operation
1 Abort channels all selected channels
6:5
-
R0
Not used
4
DMAARM4 0
R/W DMA arm channel 4
This bit must be set to 1 in order for any byte/word transfers to occur on the
channel. For non-repetitive transfer modes, the bit is automatically cleared when
the transfer count is reached
3
DMAARM3 0
R/W DMA arm channel 3
This bit must be set to 1 in order for any byte/word transfers to occur on the
channel. For non-repetitive transfer modes, the bit is automatically cleared when
the transfer count is reached
2
DMAARM2 0
R/W DMA arm channel 2
This bit must be set to 1 in order for any byte/word transfers to occur on the
channel. For non-repetitive transfer modes, the bit is automatically cleared when
the transfer count is reached
1
DMAARM1 0
R/W DMA arm channel 1
This bit must be set to 1 in order for any byte/word transfers to occur on the
channel. For non-repetitive transfer modes, the bit is automatically cleared when
the transfer count is reached
0
DMAARM0 0
R/W DMA arm channel 0
This bit must be set to 1 in order for any byte/word transfers to occur on the
channel. For non-repetitive transfer modes, the bit is automatically cleared when
the transfer count is reached
SWRS055F
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