CC2510F16 Datasheet, PDF (47/244 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller

Register
Name
U0GCR
U1CSR
U1DBUF
U1BAUD
U1UCR
U1GCR
ENDIAN
WDCTL
CC2510Fx / CC2511Fx
SFR
Module
Address
0xC5
USART0
0xF8
USART1
0xF9
USART1
0xFA
USART1
0xFB
USART1
0xFC
USART1
0x95
MEMORY
0xC9
WDT
Description
USART 0 Generic Control
USART 1 Control and Status
USART 1 Receive/Transmit Data Buffer
USART 1 Baud Rate Control
USART 1 UART Control
USART 1 Generic Control
USB Endianess Control (CC2511Fx)
Watchdog Timer Control
Retention⁶
Y
Y
Y
Y
Y,[7]N
Y
Y
Y
Table 31: CC2510Fx/CC2511Fx Specific SFR Overview
10.2.3.4 Radio Registers
The radio registers are all related to Radio
configuration and control. The RF registers can
only be accessed through XDATA memory
space and reside in address range 0xDF00 -
0xDF3D.
Table 32 gives a descriptive overview of these
registers. Each register is described in detail in
Section 13.18, starting on Page 208.
XDATA
Address
0xDF00
0xDF01
0xDF02
0xDF03
0xDF04
0xDF05
0xDF06
0xDF07
0xDF08
0xDF09
0xDF0A
0xDF0B
0xDF0C
0xDF0D
0xDF0E
0xDF0F
0xDF10
0xDF11
0xDF12
0xDF13
0xDF14
0xDF15
Register
SYNC1
SYNC0
PKTLEN
PKTCTRL1
PKTCTRL0
ADDR
CHANNR
FSCTRL1
FSCTRL0
FREQ2
FREQ1
FREQ0
MDMCFG4
MDMCFG3
MDMCFG2
MDMCFG1
MDMCFG0
DEVIATN
MCSM2
MCSM1
MCSM0
FOCCFG
Description
Sync word, high byte
Sync word, low byte
Packet length
Packet automation control
Packet automation control
Device address
Channel number
Frequency synthesizer control
Frequency synthesizer control
Frequency control word, high byte
Frequency control word, middle byte
Frequency control word, low byte
Modem configuration
Modem configuration
Modem configuration
Modem configuration
Modem configuration
Modem deviation setting
Main Radio Control State Machine configuration
Main Radio Control State Machine configuration
Main Radio Control State Machine configuration
Frequency Offset Compensation configuration
Retention⁷
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
7 _{Registers without retention are in their reset state after PM2 or PM3. This is only applicable for}
registers / bits that are defined as R/W
SWRS055F
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