CC2510F16 Datasheet, PDF (61/244 Pages) Texas Instruments – Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller

CC2510Fx / CC2511Fx
IEN2 (0x9A) - Interrupt Enable 2 Register
Bit Field Name
7:6
Reset
0
R/W
R/W
Description
Not used
5 _WDTIE
0
4 _P1IE
0
3 _{UTX1IE /} 0
I2STXIE
2 _UTX0IE
0
1 _{P2IE /}
0
USBIE
0 _RFIE
0
R/W Watchdog timer interrupt enable
0 Interrupt disabled
1 Interrupt enabled
R/W Port 1 interrupt enable
0 Interrupt disabled
1 Interrupt enabled
R/W USART1 TX interrupt enable / I²S TX interrupt enable
0 Interrupt disabled
1 Interrupt enabled
R/W USART0 TX interrupt enable
0 Interrupt disabled
1 Interrupt enabled
R/W Port 2 interrupt enable (Also used for USB interrupt enable on CC2511Fx)
0 Interrupt disabled
1 Interrupt enabled
R/W RF general interrupt enable
0 Interrupt disabled
1 Interrupt enabled
10.5.2 Interrupt Processing
When an interrupt occurs, the CPU will vector
to the interrupt vector address shown in Table
39, if this particular interrupt has been
enabled. Once an interrupt service has begun,
it can be interrupted only by a higher priority
interrupt. The interrupt service is terminated by
a RETI (return from interrupt) instruction.
When a RETI is performed, the CPU will return
to the instruction that would have been next
when the interrupt occurred.
When the interrupt condition occurs, an
interrupt flag bit will be set in one of the CPU
interrupt flag registers and in the peripherals
interrupt flag register, if this is available. These
bits are asserted regardless of whether the
interrupt is enabled or disabled. If the interrupt
is enabled when an interrupt flag is asserted,
then on the next instruction cycle the interrupt
will be acknowledged by hardware forcing an
LCALL to the appropriate vector address.
Interrupt response will require a varying
amount of time depending on the state of the
CPU when the interrupt occurs. If the CPU is
performing an interrupt service with equal or
greater priority, the new interrupt will be
pending until it becomes the interrupt with
highest priority. In other cases, the response
time depends on the current instruction. The
fastest possible response to an interrupt is
seven instruction cycles. This includes one
machine cycle for detecting the interrupt and
six cycles to perform the LCALL.
Clearing interrupt flags must be done correctly
to ensure that no interrupts are lost or
processed more than once. For pulsed or
edge shaped interrupt sources one should
clear the CPU interrupt flag prior to clearing
the module interrupt flag, if available, for flags
that are not automatically cleared. For level
triggered interrupts (port interrupts) one has to
clear the module interrupt flag prior to clearing
the CPU interrupt flag. When handling
interrupts where the CPU interrupt flag is
cleared by hardware, the software should only
clear the module interrupt flag. The following
interrupts are cleared by hardware:
• RFTXRX
• T1
• ADC
• T2
• URX0
• T3
• URX1/I2SRX • T4
One or more module flags can be cleared at
once. However the safest approach is to only
handle one interrupt source each time the
interrupt is triggered, hence clearing only one
SWRS055F
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