SM320C6201_15 Datasheet, PDF (64/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1^†‡ (see Figure 36)
(’C6201B)
’C6201B-150
’C6201B-200
NO.
MASTER
SLAVE
UNIT
MIN MAX
MIN MAX
4
t_su(DRV-CKXH)
Setup time, DR valid before CLKX high
12
3P -- 2
ns
5
t_h(CKXH-DRV)
Hold time, DR valid after CLKX high
4
5 + 6P
ns
† _{The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency}
in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1^†‡
(see Figure 36) (’C6201B)
NO.
1
t_h(CKXH-FXL)
2
t_d(FXL-CKXL)
PARAMETER
Hold time, FSX low after CLKX high^¶
Delay time, FSX low to CLKX low^#
Delay time, CLKX low to DX valid
’C6201B-150
’C6201B-200
MASTER^§
SLAVE
MIN MAX
MIN MAX
T -- 2 T + 3
H -- 2 H + 3
UNIT
ns
ns
3
t_d(CKXL-DXV)
6
t_{dis(CKXH-DXHZ)}
This is also specified by design but not tested to be the delay
--2
4 3P + 4 5P + 17 ns
time for data to be low impedance on the first data bit.
Disable time, DX high impedance following last data bit from
CLKX high
H -- 2 H + 3
ns
7
t_{dis(FXH-DXHZ)}
Disable time, DX high impedance following last data bit from
FSX high
P + 3 3P + 17 ns
8
t_d(FXL-DXV)
Delay time, FSX low to DX valid
2P + 2 4P + 17 ns
† _{The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency}
in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
§ _{T = CLKX period = (1 + CLKGDV) * P; if CLKSM = 1, then P = 1/CPU clock frequency}
= CLKX period = (1 + CLKGDV) * P_clks; if CLKSM = 0, then P_clks = CLKS period.
H = CLKX high pulse width = (CLKGDV/2 + 1) * T
L = CLKX low pulse width = (CLKGDV/2) * T
¶ _{FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX}
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(CLKX).
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