SM320C6201_15 Datasheet, PDF (36/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 15)
NO.
7
t_{su(EDV-SSCLKH)}
8
t_{h(SSCLKH-EDV)}
Setup time, read EDx valid before SSCLK high
Hold time, read EDx valid after SSCLK high
’C6201-150
MIN MAX
1.5
1.2
’C6201B-150
’C6201B-200
MIN MAX
1.5
1.5
UNIT
ns
ns
switching characteristics for synchronous-burst SRAM cycles^† (full-rate SSCLK)
(see Figure 15 and Figure 16)
NO.
PARAMETER
’C6201-150
MIN MAX
’C6201B-150
’C6201B-200
MIN MAX
UNIT
1
t_{su(CEV-SSCLKH)}
Setup time, CEx valid before SSCLK high
P -- 4.7
0.5P -- 1.3
ns
2
t_{oh(SSCLKH-CEV)}
Output hold time, CEx valid after SSCLK high
0
0.5P -- 2.3
ns
3
t_{su(BEV-SSCLKH)}
Setup time, BEx valid before SSCLK high
P -- 4.7
0.5P -- 1.3
ns
4
t_{oh(SSCLKH-BEIV)}
Output hold time, BEx invalid after SSCLK high
1*
0.5P -- 2.3
ns
5
t_{su(EAV-SSCLKH)}
Setup time, EAx valid before SSCLK high
P -- 5.7
0.5P -- 1.3
ns
6
t_{oh(SSCLKH-EAIV)}
Output hold time, EAx invalid after SSCLK high
1*
0.5P -- 2.3
ns
9
t_{su(ADSV-SSCLKH)}
Setup time, SSADS valid before SSCLK high
P -- 3.7
0.5P -- 1.3
ns
10 t_{oh(SSCLKH-ADSV)}
Output hold time, SSADS valid after SSCLK high
0
0.5P -- 2.3
ns
11 t_{su(OEV-SSCLKH)}
Setup time, SSOE valid before SSCLK high
P -- 4.7
0.5P -- 1.3
ns
12 t_{oh(SSCLKH-OEV)}
Output hold time, SSOE valid after SSCLK high
0
0.5P -- 2.3
ns
13 t_{su(EDV-SSCLKH)}
Setup time, EDx valid before SSCLK high
P -- 4.7
0.5P -- 1.3
ns
14 t_{oh(SSCLKH-EDIV)}
Output hold time, EDx invalid after SSCLK high
1*
0.5P -- 2.3
ns
15 t_{su(WEV-SSCLKH)}
Setup time, SSWE valid before SSCLK high
P -- 3.7
0.5P -- 1.3
ns
16 t_{oh(SSCLKH-WEV)}
Output hold time, SSWE valid after SSCLK high
0
0.5P -- 2.3
ns
† _{The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SSCLK duty cycle.}
P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.
*This parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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