SM320C6201_15 Datasheet, PDF (37/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
SSCLK
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SSADS
SSOE
SSWE
1
3
BE1
5
A1
9
11
2
4
BE2 BE3 BE4
6
A2
A3
A4
8
7
Q1
Q2
Q3
Q4
10
12
Figure 15. SBSRAM Read Timing (Full-Rate SSCLK)
SSCLK
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SSADS
SSOE
SSWE
1
3
BE1
5
A1
D1
9
2
BE2
BE3
A2
A3
13
D2
D3
4
BE4
6
A4
14
D4
10
15
16
Figure 16. SBSRAM Write Timing (Full-Rate SSCLK)
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