SM320C6201_15 Datasheet, PDF (43/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
SYNCHRONOUS DRAM TIMING (CONTINUED)
SDCLK
1
2
CEx
BE[3:0]
4
3
BE1
BE2
BE3
6
5
EA[15:2]
CA1
CA2
CA3
7
8
ED[31:0]
15
D1
D2
D3
SDA10
SDRAS
9
10
SDCAS
SDWE
Figure 19. Three SDRAM Read Commands
SDCLK
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
SDWE
1
3
4
BE1
BE2
5
6
CA1
CA2
11
D1
D2
15
2
BE3
CA3
12
D3
9
10
13
14
Figure 20. Three SDRAM WRT Commands
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