SM320C6201_15 Datasheet, PDF (32/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics for CLKOUT2^† (see Figure 11)
NO.
PARAMETER
1
t_c(CKO2)
Cycle time, CLKOUT2
2
t_w(CKO2H)
Pulse duration, CLKOUT2 high
3
t_w(CKO2L)
Pulse duration, CLKOUT2 low
4
t_t(CKO2)
Transition time, CLKOUT2
† _{P = 1/CPU clock frequency in ns.}
*This parameter is not production tested.
’C6201-150
MIN
2P -- 0.7*
P -- 0.7*
P -- 0.7*
MAX
2P + 0.7*
P + 0.7*
P + 0.7*
0.6*
CLKOUT2
1
4
2
3
Figure 11. CLKOUT2 Timings
’C6201B-150
’C6201B-200
MIN
MAX
2P -- 0.7 2P + 0.7
P -- 0.7
P + 0.7
P -- 0.7
P + 0.7
0.6
UNIT
ns
ns
ns
ns
4
SDCLK, SSCLK timing parameters
SDCLK timing parameters are the same as CLKOUT2 parameters.
SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK
configuration.
switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1
(see Figure 12)^†
NO.
PARAMETER
1
t_{d(CKO1-SSCLK)}
2
t_{d(CKO1-SSCLK1/2)}
Delay time, CLKOUT1 edge to SSCLK edge
Delay time, CLKOUT1 edge to SSCLK edge
(1/2 clock rate)
3
t_d(CKO1-CKO2)
Delay time, CLKOUT1 edge to CLKOUT2 edge
4
t_{d(CKO1-SDCLK)}
Delay time, CLKOUT1 edge to SDCLK edge
† _{P = 1/CPU clock frequency in ns.}
*This parameter is not production tested.
’C6201-150
MIN MAX
--1.2* 1.6*
’C6201B-150
’C6201B-200
MIN
MAX
(P/2) + 0.2 (P/2) + 4.2
UNIT
ns
--1.0* 2.4* (P/2) -- 1 (P/2) + 2.4 ns
--1.0* 2.4* (P/2) -- 1 (P/2) + 2.4 ns
--1.0* 2.4* (P/2) -- 1 (P/2) + 2.4 ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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