SM320C6201_15 Datasheet, PDF (46/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles^† (see Figure 25)
NO.
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN MAX MIN MAX
1
t_{su(HOLDH-CKO1H)}
Setup time, HOLD high before CLKOUT1 high
5*
1
ns
2
t_{h(CKO1H-HOLDL)}
Hold time, HOLD low after CLKOUT1 high
2*
4
ns
† _{HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle.}
Thus, HOLD can be an asynchronous input.
*This parameter is not production tested.
switching characteristics for the HOLD/HOLDA cycles (see Figure 25)
NO.
PARAMETER
’C6201-150
MIN MAX
’C6201B-150
’C6201B-200
MIN MAX
UNIT
3
t_R(HOLDL-BHZ)
Response time, HOLD low to EMIF Bus high impedance
4*
‡
4
‡ ^CLKOUT1
cycles
4
t_{R(BHZ-HOLDAL)}
Response time, EMIF Bus high impedance to HOLDA low
1*
2*
1
2
CLKOUT1
cycles
5
t_{R(HOLDH-HOLDAH)}
Response time, HOLD high to HOLDA high
4*
6
4
7
CLKOUT1
cycles
6
t_{d(CKO1H-HOLDAL)}
7
t_d(CKO1H-BHZ)
8
t_d(CKO1H-BLZ)
9
t_R(HOLDH-BLZ)
Delay time, CLKOUT1 high to HOLDA valid
Delay time, CLKOUT1 high to EMIF Bus high impedance^§
Delay time, CLKOUT1 high to EMIF Bus low impedance^§
Response time, HOLD high to EMIF Bus low impedance
--1*
5
--1*
5*
--1*
5*
3*
5*
1
8
ns
3
11
ns
3
11
ns
3
6
CLKOUT1
cycles
*This parameter is not production tested.
‡ _{All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write}
with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then
the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
§ _{EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.}
DSP Owns Bus
External Requester
DSP Owns Bus
CLKOUT1
HOLD
4
3
2
1
6
5
9
2
1
6
HOLDA
7
EMIF Bus^†
’C62x
Ext Req
8
’C62x
† _{EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.}
Figure 25. HOLD/HOLDA Timing
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design phase of development. Characteristic data and other
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