SM320C6201_15 Datasheet, PDF (51/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
HOST-PORT INTERFACE TIMING (CONTINUED)
HAS
1
HCNTL[1:0]
1
HR/W
1
HHWIL
HSTROBE^†
2
2
2
3
1
2
1
2
1
2
4
3
HCS
HD[15:0] (output)
15
7
9
15
16
9
5
HRDY (case 1)
1st half-word
8
2nd half-word
17
5
6
8
HRDY (case 2)
5
17
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
Figure 28. HPI Read Timing (HAS Not Used, Tied High)
HAS
10
HCNTL[1:0]
10
HR/W
10
HHWIL
HSTROBE^†
11
11
11
3
11
10
11
10
11
10
4
3
HCS
15
15
7
9
16
9
HD[15:0] (output)
5
1st half-word
8
2nd half-word
17
5
HRDY (case 1)
6
8
17
5
HRDY (case 2)
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
Figure 29. HPI Read Timing (HAS Used)
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