SM320C6201_15 Datasheet, PDF (52/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
HOST-PORT INTERFACE TIMING (CONTINUED)
HAS
1
2
1
2
HCNTL[1:0]
12
12
13
13
HBE[1:0]
1
2
1
2
HR/W
1
2
1
2
HHWIL
HSTROBE^†
3
3
4
14
HCS
12
12
13
13
HD[15:0] (input)
5
1st half-word
2nd half-word
17
5
HRDY
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
Figure 30. HPI Write Timing (HAS Not Used, Tied High)
HAS
HBE[1:0]
12
13
12
13
11
10
HCNTL[1:0]
11
10
11
10
HR/W
11
10
11
10
HHWIL
11
10
HSTROBE^†
3
3
4
14
HCS
HD[15:0] (input)
12
13
12
13
5
HRDY
1st half-word
2nd half-word
17
5
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
Figure 31. HPI Write Timing (HAS Used)
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