SM320C6201_15 Datasheet, PDF (21/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
clock PLL
All of the ’C62xx clocks are generated from a single source through the CLKIN pin. This source clock either
drives the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock.
To use the PLL to generate the CPU clock, the filter circuit shown in Figure 5 must be properly designed. Note
that for ’C6201, the EMI filter must be powered by the core voltage (2.5 V), and for ’C6201B, it must be powered
by the I/O voltage (3.3 V).
To configure the ’C62xx PLL clock for proper operation, see Figure 5 and Table 1. To minimize the clock jitter,
a single clean power supply should power both the ’C62x device and the external clock oscillator circuit. The
minimum CLKIN rise and fall times should also be observed. See the input and output clocks section for input
clock timing requirements.
’C6201 CLKOUT1 Frequency Range 40--200 MHz -- 0 1 0 -- ’C6201B CLKOUT1 Frequency Range 130--233 MHz
’C6201 CLKOUT1 Frequency Range 35--160 MHz -- 0 0 1 -- ’C6201B CLKOUT1 Frequency Range 65--200 MHz
’C6201 CLKOUT1 Frequency Range 25--135 MHz -- 0 0 0 -- ’C6201B CLKOUT1 Frequency Range 50--140 MHz
3.3 V 2.5 V 3 OUT
PLLV
PLLF
R1
1 IN
2
GND
10 μF 0.1 μF C1 C2
(Bypass)
PLLG
CLKIN
’320C6201/C6201B
EMIF
CLKOUT
CLKOUT1
CLKOUT2
SSCLK
SDCLK
1 1 -- MULT×4
0 1 -- Reserved
1 0 -- Reserved
0 0 -- MULT×1
f(CLKOUT)=f(CLKIN)×4
f(CLKOUT)=f(CLKIN)
NOTES: A. For the ’C6201 CLKMODE x4, values for C1, C2, and R1 depend on CLKIN and CLKOUT frequencies.
For the ’C6201B CLKMODE x4, values for C1, C2, and R1 are fixed and apply to all valid frequency ranges of CLKIN and CLKOUT.
B. For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal has
to be connected to a clean supply and the PLLG and PLLF terminals should be tied together.
C. Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1
frequency. Choose the lowest frequency range that includes the desired frequency. For example, CLKOUT1 = 133 MHz, a
PLLFREQ value of 000b should be used for both the ’C6201 and the ’C6201B. For CLKOUT1 = 200 MHz, PLLFREQ should be set
to 010b for the ’C6201 or 001b for the ’C6201B. PLLFREQ values other than 000b, 001b, and 010b are reserved.
D. EMI filter manufacturer TDK part number ACF451832-153-T
E. For the ’C6201B, the 3.3-V supply for the EMI filter (and PLLV) must be from the same 3.3-V power plane supplying the I/O voltage,
DV_DD.
Figure 5. PLL Block Diagram
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