SM320C6201_15 Datasheet, PDF (17/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

signal groups (continued)
32
ED[31:0]
CE3
CE2
CE1
CE0
EA[21:2]
20
BE3
BE2
BE1
BE0
HOLD
HOLDA
SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
Data
Memory Map
Space Select
Word Address
Asynchronous
Memory
Control
SBSRAM
Control
Byte Enables
HOLD/
HOLDA
SDRAM
Control
EMIF
(External Memory Interface)
ARE
AOE
AWE
ARDY
SSADS
SSOE
SSWE
SSCLK
SDA10
SDRAS
SDCAS
SDWE
SDCLK
TOUT1
TINP1
CLKX1
FSX1
DX1
CLKR1
FSR1
DR1
CLKS1
Timer 1
Timers
Timer 0
McBSP1
Transmit
McBSP0
Transmit
Receive
Receive
Clock
Clock
McBSPs
(Multichannel Buffered Serial Ports)
Figure 2. Peripheral Signals
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TOUT0
TINP0
CLKX0
FSX0
DX0
CLKR0
FSR0
DR0
CLKS0
17