SM320C6201_15 Datasheet, PDF (53/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP^†‡(see Figure 32)
NO.
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN MAX MIN MAX
2
t_c(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2*
2
CLKOUT1
cycles
3
t_w(CKRX)
Pulse duration, CLKR/X high or CLKR/X
low
CLKR/X ext P -- 1*
P -- 1
ns
Setup time, external FSR high before
CLKR int
13
9
5
t_su(FRH-CKRL)
CLKR low
ns
CLKR ext
4
1
Hold time, external FSR high after CLKR ^{CLKR int}
7*
6
6
t_h(CKRL-FRH)
low
ns
CLKR ext
3.5
3
CLKR int
13.5
8
7
t_su(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR ext
1
0
ns
CLKR int
4*
3
8
t_h(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR ext
4
3
ns
Setup time, external FSX high before
CLKX int
13
9
10 t_su(FXH-CKXL)
CLKX low
ns
CLKX ext
4
1
Hold time, external FSX high after CLKX ^{CLKX int}
7
6
11 t_h(CKXL-FXH)
low
ns
CLKX ext
3.5
3
† _{CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.}
‡ _{The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SSCLK duty cycle.}
P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.
*This parameter is not production tested.
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design phase of development. Characteristic data and other
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change or discontinue these products without notice.
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