SM320C6201_15 Datasheet, PDF (56/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 33)
NO.
1
t_su(FRH-CKSH)
Setup time, FSR high before CLKS high
2
t_h(CKSH-FRH)
Hold time, FSR high after CLKS high
*This parameter is not production tested.
’C6201-150
MIN MAX
4*
4*
’C6201B-150
’C6201B-200
MIN MAX
4
4
UNIT
ns
ns
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X(needs resync)
1
2
Figure 33. FSR Timing When GSYNC = 1
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design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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