SM320C6201_15 Datasheet, PDF (48/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
RESET TIMING (CONTINUED)
CLKOUT1
RESET
CLKOUT2
SDCLK
SSCLK
LOW GROUP^†
HIGH GROUP^†
Z GROUP^†
† _{Low group consists of:}
High group consists of:
Z group consists of:
1
2
2
3
4
5
6
7
8
9
10
11
12
13
14
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
HRDY and HINT
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
Figure 26. Reset Timing
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