SM320C6201_15 Datasheet, PDF (49/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
EXTERNAL INTERRUPT/RESET TIMING
timing requirements for interrupt response cycles^† (see Figure 27)
NO.
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN MAX MIN MAX
3
t_w(ILOW)
Width of the interrupt pulse low
2
2
CLKOUT1
cycles
4
t_w(IHIGH)
Width of the interrupt pulse high
2
2
CLKOUT1
cycles
† _{Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can}
be connected to asynchronous inputs.
switching characteristics during interrupt response cycles (see Figure 27)
NO.
PARAMETER
’C6201-150
MIN MAX
1
t_{R(EINTH-IACKH)}
Response time, EXT_INTx high to IACK high
9^‡*
2
t_R(ISFP)
Response time, interrupt service fetch packet execution after
EXT_INTx high
11^‡*
5
t_{d(CKO2L-IACKV)}
6
t_{d(CKO2L-INUMV)}
Delay time, CLKOUT2 low to IACK valid
Delay time, CLKOUT2 low to INUMx valid
0*
10
0*
10
7
t_{d(CKO2L-INUMIV)}
Delay time, CLKOUT2 low to INUMx invalid
0* 10*
‡ _{Add two CLKOUT1 cycles to this parameter if the interrupt is recognized during the high half of CLKOUT2}
*This parameter is not production tested.
’C6201B-150
’C6201B-200
MIN MAX
9^‡
11^‡
0
10
0
10
0
10
UNIT
CLKOUT1
cycles
CLKOUT1
cycles
ns
ns
ns
CLKOUT1
EXT_INTx, NMI
Interrupt Flag
IACK
INUMx
CLKOUT2
1 2 3 4 5 PG PS PW PR DP DC
E1
1
2
4
3
5
5
6
7
Interrupt Number
Figure 27. Interrupt Timing
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