SM320C6201_15 Datasheet, PDF (30/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN^† (see Figure 9) (’C6201)
’C6201-150
NO.
CLKMODE CLKMODE
= x4
= x1
MIN MAX MIN MAX
1 t_c(CLKIN)
Cycle time, CLKIN
24*
2 t_w(CLKINH) Pulse duration, CLKIN high
9.8*
3 t_w(CLKINL) Pulse duration, CLKIN low
9.8*
4 t_t(CLKIN)
Transition time, CLKIN
† _{The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH.}
*This parameter is not production tested.
6.67
2.7*
2.7*
5*
0.6*
UNIT
ns
ns
ns
ns
timing requirements for CLKIN (see Figure 9) (’C6201B)
NO.
1 t_c(CLKIN)
2 t_w(CLKINH)
3 t_w(CLKINL)
4 t_t(CLKIN)
Cycle time, CLKIN
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
’C6201B-150
CLKMODE CLKMODE
= x4
= x1
MIN MAX MIN MAX
24
6.67
9.8
2.7
9.8
2.7
5
0.6
’C6201B-200
CLKMODE CLKMODE
= x4
= x1
MIN MAX MIN MAX
20
5
8
2.25
8
2.25
5
0.6
UNIT
ns
ns
ns
ns
CLKIN
1
4
2
3
4
Figure 9. CLKIN Timings
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