SM320C6201_15 Datasheet, PDF (50/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
HOST-PORT INTERFACE TIMING
timing requirements for host-port interface cycles^† (see Figure 28, Figure 29, Figure 30, and
Figure 31)
NO.
1
t_{su(SEL-HSTBL)}
2
t_h(HSTBL-SEL)
Setup time, select signals^‡ valid before HSTROBE low
Hold time, select signals^‡ valid after HSTROBE low
’C6201-150
MIN MAX
1
2
’C6201B-150
’C6201B-200
MIN MAX
1
2
3
t_w(HSTBL)
Pulse duration, HSTROBE low
2
2
Pulse duration, HSTROBE high between consecutive
4
t_w(HSTBH)
accesses
2*
2
10 t_su(SEL-HASL)
11 t_h(HASL-SEL)
Setup time, select signals^‡ valid before HAS low
Hold time, select signals^‡ valid after HAS low
1
1
2
2
12 t_{su(HDV-HSTBH)}
Setup time, host data valid before HSTROBE high
1
1
13 t_h(HSTBH-HDV)
Hold time, host data valid after HSTROBE high
1
1
Hold time, HSTROBE low after HRDY low. HSTROBE
14 t_{h(HRDYL-HSTBL)}
should not be inactivated until HRDY is active (low);
1*
1
otherwise, HPI writes will not complete properly.
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
‡ _{Select signals include: HCNTRL[1:0], HR/W, and HHWIL.}
*This parameter is not production tested.
UNIT
ns
ns
CLKOUT1
cycles
CLKOUT1
cycles
ns
ns
ns
ns
ns
switching characteristics during host-port interface cycles^†§ (see Figure 28, Figure 29, Figure 30,
and Figure 31)
NO.
5
t_d(HCS-HRDY)
6
t_{d(HSTBL-HRDYH)}
7
t_{oh(HSTBL-HDLZ)}
PARAMETER
Delay time, HCS to HRDY^¶
Delay time, HSTROBE low to HRDY high^#
Output hold time, HD low impedance after HSTROBE low
for an HPI read
’C6201-150
MIN MAX
1* 7*
3* 12*
’C6201B-150
’C6201B-200
MIN MAX
17
3 12
UNIT
ns
ns
4*
4
ns
8
t_d(HDV-HRDYL)
Delay time, HD valid to HRDY low
P -- 3* P* P -- 2 P
ns
9
t_{oh(HSTBH-HDV)}
Output hold time, HD valid after HSTROBE high
3* 12*
3 12
ns
15 t_{d(HSTBH-HDHZ)}
Delay time, HSTROBE high to HD high impedance
3* 12*
3 12
ns
16 t_d(HSTBL-HDV)
Delay time, HSTROBE low to HD valid
3* 12*
3 12
ns
17 t_{d(HSTBH-HRDYH)}
Delay time, HSTROBE high to HRDY high^||
3* 12*
3 12
ns
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
§ _{The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency}
in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.
¶ _{HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy}
completing a previous HPID write or READ with autoincrement.
*This parameter is not production tested.
# _{This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the}
request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID.
|| _{This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write}
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
50
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443