SM320C6201_15 Datasheet, PDF (41/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 19) (’C6201)
NO.
7
t_{su(EDV-SDCLKH)}
8
t_{h(SDCLKH-EDV)}
Setup time, read EDx valid before SDCLK high
Hold time, read EDx valid after SDCLK high
’C6201-150
MIN MAX
3.5
1.2
UNIT
ns
ns
switching characteristics for synchronous DRAM cycles^† (see Figure 19--Figure 24) (’C6201)
NO.
PARAMETER
’C6201-150
UNIT
MIN MAX
1
t_{su(CEV-SDCLKH)}
Setup time, CEx valid before SDCLK high
P -- 4.2
ns
2
t_{oh(SDCLKH-CEV)}
Output hold time, CEx valid after SDCLK high
P -- 5.2
ns
3
t_{su(BEV-SDCLKH)}
Setup time, BEx valid before SDCLK high
P -- 4.2
ns
4
t_{oh(SDCLKH-BEIV)}
Output hold time, BEx invalid after SDCLK high
P -- 5.2*
ns
5
t_{su(EAV-SDCLKH)}
Setup time, EAx valid before SDCLK high
P -- 4.2
ns
6
t_{oh(SDCLKH-EAIV)}
Output hold time, EAx invalid after SDCLK high
P -- 5.2*
ns
9
t_{su(SDCAS-SDCLKH)}
Setup time, SDCAS valid before SDCLK high
P -- 4.2
ns
10 t_{oh(SDCLKH-SDCAS)}
Output hold time, SDCAS valid after SDCLK high
P -- 5.2
ns
11 t_{su(EDV-SDCLKH)}
Setup time, EDx valid before SDCLK high
P -- 4.2*
ns
12 t_{oh(SDCLKH-EDIV)}
Output hold time, EDx invalid after SDCLK high
P -- 5.2*
ns
13 t_{su(SDWE-SDCLKH)}
Setup time, SDWE valid before SDCLK high
P -- 4.2
ns
14 t_{oh(SDCLKH-SDWE)}
Output hold time, SDWE valid after SDCLK high
P -- 5.2
ns
15 t_{su(SDA10V-SDCLKH)}
Setup time, SDA10 valid before SDCLK high
P -- 4.2
ns
16 t_{oh(SDCLKH-SDA10IV)}
Output hold time, SDA10 invalid after SDCLK high
P -- 5.2*
ns
17 t_{su(SDRAS-SDCLKH)}
Setup time, SDRAS valid before SDCLK high
P -- 4.2
ns
18 t_{oh(SDCLKH-SDRAS)}
Output hold time, SDRAS valid after SDCLK high
P -- 5.2
ns
† _{The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SDCLK duty cycle.}
P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.
*This parameter is not production tested.
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