SM320C6201_15 Datasheet, PDF (39/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK)
(see Figure 17) (’C6201B)
NO.
7
t_{su(EDV-SSCLKH)}
8
t_{h(SSCLKH-EDV)}
Setup time, read EDx valid before SSCLK high
Hold time, read EDx valid after SSCLK high
’C6201B-150
MIN MAX
4.2
1.5
’C6201B-200
MIN MAX
2.5
1.5
UNIT
ns
ns
switching characteristics for synchronous-burst SRAM cycles^† (half-rate SSCLK)
(see Figure 17 and Figure 18) (’C6201B)
NO.
PARAMETER
’C6201B-150
MIN
MAX
’C6201B-200
MIN
MAX
UNIT
1
t_{su(CEV-SSCLKH)}
Setup time, CEx
valid before SSCLK high
1.5P -- 5.5
1.5P -- 3
ns
2
t_{oh(SSCLKH-CEV)}
Output hold time, CEx valid
after SSCLK high
0.5P -- 2.4
0.5P -- 1.5
ns
3
t_{su(BEV-SSCLKH)}
Setup time, BEx
valid before SSCLK high
1.5P -- 5.5
1.5P -- 3
ns
4
t_{oh(SSCLKH-BEIV)}
Output hold time, BEx invalid after SSCLK high
0.5P -- 2.4
0.5P -- 1.5
ns
5
t_{su(EAV-SSCLKH)}
Setup time, EAx
valid before SSCLK high
1.5P -- 5.5
1.5P -- 3
ns
6
t_{oh(SSCLKH-EAIV)}
Output hold time, EAx invalid after SSCLK high
0.5P -- 2.4
0.5P -- 1.5
ns
9
t_{su(ADSV-SSCLKH)}
Setup time, SSADS valid
before SSCLK high
1.5P -- 5.5
1.5P -- 3
ns
10 t_{oh(SSCLKH-ADSV)}
Output hold time, SSADS valid after SSCLK high
0.5P -- 2.4
0.5P -- 1.5
ns
11 t_{su(OEV-SSCLKH)}
Setup time, SSOE valid before SSCLK high
1.5P -- 5.5
1.5P -- 3
ns
12 t_{oh(SSCLKH-OEV)}
Output hold time, SSOE valid after SSCLK high
0.5P -- 2.4
0.5P -- 1.5
ns
13 t_{su(EDV-SSCLKH)}
Setup time, EDx valid before SSCLK high
1.5P -- 5.5
1.5P -- 3
ns
14 t_{oh(SSCLKH-EDIV)}
Output hold time, EDx invalid after SSCLK high
0.5P -- 2.4
0.5P -- 1.5
ns
15 t_{su(WEV-SSCLKH)}
Setup time, SSWE valid before SSCLK high
1.5P -- 5.5
1.5P -- 3
ns
16 t_{oh(SSCLKH-WEV)}
Output hold time, SSWE valid after SSCLK high
0.5P -- 2.4
0.5P -- 1.5
ns
† _{The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter or SSCLK duty cycle.}
P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.67 ns.
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change or discontinue these products without notice.
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