SM320C6201_15 Datasheet, PDF (47/76 Pages) Texas Instruments – DIGITAL SIGNAL PROCESSORS

SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
RESET TIMING
SGUS028A -- NOVEMBER 1998 -- REVISED JANUARY 1999
timing requirements for reset (see Figure 26)
NO.
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN MAX MIN MAX
1
t_w(RST)
Width of the RESET pulse (PLL stable)
Width of the RESET pulse (PLL needs to sync up)^†
10*
250^*
10
CLKOUT1
cycles
250
μs
*This parameter is not production tested.
† _{The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 μs to stabilize following device}
powerup or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the
clock PLL section for PLL lock times.
switching characteristics during reset^‡ (see Figure 26)
NO.
PARAMETER
’C6201-150
MIN MAX
’C6201B-150
’C6201B-200
MIN MAX
UNIT
2
t_R(RST)
Response time to change of value in RESET signal
2
2
CLKOUT1
cycles
3
t_{d(CKO1H-CKO2IV)}
Delay time, CLKOUT1 high to CLKOUT2 invalid
--1* 10*
--1
10
ns
4
t_{d(CKO1H-CKO2V)}
Delay time, CLKOUT1 high to CLKOUT2 valid
--1*
10
--1
10
ns
5
t_{d(CKO1H-SDCLKIV)}
Delay time, CLKOUT1 high to SDCLK invalid
--1* 10*
--1
10
ns
6
t_{d(CKO1H-SDCLKV)}
Delay time, CLKOUT1 high to SDCLK valid
--1*
10
--1
10
ns
7
t_{d(CKO1H-SSCKIV)}
Delay time, CLKOUT1 high to SSCLK invalid
--1* 10*
--1
10
ns
8
t_{d(CKO1H-SSCKV)}
Delay time, CLKOUT1 high to SSCLK valid
--1*
10
--1
10
ns
9
t_{d(CKO1H-LOWIV)}
Delay time, CLKOUT1 high to low group invalid
--1* 10*
--1
10
ns
10 t_{d(CKO1H-LOWV)}
Delay time, CLKOUT1 high to low group valid
--1*
--1
ns
11 t_{d(CKO1H-HIGHIV)}
Delay time, CLKOUT1 high to high group invalid
--1* 10*
--1
10
ns
12 t_{d(CKO1H-HIGHV)}
Delay time, CLKOUT1 high to high group valid
--1*
--1
ns
13 t_d(CKO1H-ZHZ)
Delay time, CLKOUT1 high to Z group high impedance
--1* 10*
--1
10
ns
14 t_d(CKO1H-ZV)
Delay time, CLKOUT1 high to Z group valid
--1*
--1
ns
‡ _{Low group consists of:}
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
High group consists of:
HRDY and HINT
Z group consists of:
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
*This parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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