LM3S6611 Datasheet, PDF (578/647 Pages) List of Unclassifed Manufacturers – Microcontroller

Signal Tables
Table 17-5. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
B10
CMOD1
I
TTL
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
PE2
I/O
TTL
GPIO port E bit 2.
B11
SSI1Rx
I
TTL
SSI module 1 receive.
PE1
B12
SSI1Fss
I/O
TTL
GPIO port E bit 1.
I/O
TTL
SSI module 1 frame signal.
C1
PE7
I/O
TTL
GPIO port E bit 7.
PE6
I/O
TTL
GPIO port E bit 6.
C2
C1o
O
TTL
Analog comparator 1 output.
C3
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
C4
GND
-
Power Ground reference for logic and I/O pins.
C5
GND
-
Power Ground reference for logic and I/O pins.
VDDA
C6
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 593, regardless of system implementation.
VDDA
C7
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 593, regardless of system implementation.
C8
GNDPHY
-
Power GND of the Ethernet PHY.
C9
GNDPHY
-
Power GND of the Ethernet PHY.
C10
VCCPHY
-
Power VCC of the Ethernet PHY.
PB2
C11
I2C0SCL
I/O
TTL
GPIO port B bit 2.
I/O
OD
I²C module 0 clock.
PB3
C12
I2C0SDA
I/O
TTL
GPIO port B bit 3.
I/O
OD
I²C module 0 data.
D1
PE4
I/O
TTL
GPIO port E bit 4.
D2
PE5
I/O
TTL
GPIO port E bit 5.
D3
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
D10
VCCPHY
-
Power VCC of the Ethernet PHY.
D11
VCCPHY
-
Power VCC of the Ethernet PHY.
PB1
D12
CCP2
I/O
TTL
GPIO port B bit 1.
I/O
TTL
Capture/Compare/PWM 2.
E1
PD4
I/O
TTL
GPIO port D bit 4.
E2
PD5
I/O
TTL
GPIO port D bit 5.
LDO
E3
-
Power Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. The LDO
pin must also be connected to the VDD25 pins at the board level
in addition to the decoupling capacitor(s).
578
July 16, 2014
Texas Instruments-Production Data