LM3S6611 Datasheet, PDF (20/647 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 445
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 447
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 448
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 450
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 451
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 452
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 453
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 454
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 455
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 456
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 457
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 458
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 459
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 460
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 461
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 462
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 463
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 464
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 465
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 481
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 482
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 486
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 487
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 488
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 489
I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 490
I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 491
I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 492
I²C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 494
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
I²C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 495
I²C Slave Data (I2CSDR), offset 0x808 ........................................................................... 497
I²C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 498
I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 499
I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 500
Register 16: I²C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 501
Ethernet Controller ...................................................................................................................... 502
Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 ....... 514
Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 517
Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 518
Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 519
Register 5: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 520
Register 6: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 522
Register 7: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 523
Register 8: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 524
Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 526
Register 10: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 527
Register 11: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 528
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July 16, 2014
Texas Instruments-Production Data