LM3S6611 Datasheet, PDF (568/647 Pages) List of Unclassifed Manufacturers – Microcontroller

Signal Tables
Table 17-1. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PB6
I/O
TTL
GPIO port B bit 6.
90
C0+
I
Analog Analog comparator 0 positive input.
PB5
I/O
TTL
GPIO port B bit 5.
91
C1-
I
Analog Analog comparator 1 negative input.
PB4
I/O
TTL
GPIO port B bit 4.
92
C0-
I
Analog Analog comparator 0 negative input.
93
VDD
-
Power Positive supply for I/O and some logic.
94
GND
-
Power Ground reference for logic and I/O pins.
95
PD4
I/O
TTL
GPIO port D bit 4.
96
PD5
I/O
TTL
GPIO port D bit 5.
GNDA
97
-
Power The ground reference for the analog circuits ( Analog Comparators,
etc.). These are separated from GND to minimize the electrical
noise contained on VDD from affecting the analog functions.
VDDA
98
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 593, regardless of system implementation.
99
PD6
I/O
TTL
GPIO port D bit 6.
PD7
100
CCP1
I/O
TTL
GPIO port D bit 7.
I/O
TTL
Capture/Compare/PWM 1.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
17.1.2 Signals by Signal Name
Table 17-2. Signals by Signal Name
Pin Name
C0+
C0-
C0o
C1+
C1-
C1o
CCP0
CCP1
CCP2
CCP3
CCP4
CCP5
CMOD0
Pin Number
90
92
24
24
91
2
66
100
67
23
22
25
65
Pin Type
I
I
O
I
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I
CMOD1
76
I
Buffer Type^a Description
Analog Analog comparator 0 positive input.
Analog Analog comparator 0 negative input.
TTL
Analog comparator 0 output.
Analog Analog comparator 1 positive input.
Analog Analog comparator 1 negative input.
TTL
Analog comparator 1 output.
TTL
Capture/Compare/PWM 0.
TTL
Capture/Compare/PWM 1.
TTL
Capture/Compare/PWM 2.
TTL
Capture/Compare/PWM 3.
TTL
Capture/Compare/PWM 4.
TTL
Capture/Compare/PWM 5.
TTL
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
TTL
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
568
July 16, 2014
Texas Instruments-Production Data