LM3S6611 Datasheet, PDF (519/647 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S6611 Microcontroller
Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C
This register configures the transmitter and controls the frames that are transmitted.
Ethernet MAC Transmit Control (MACTCTL)
Base 0x4004.8000
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DUPLEX reserved CRC PADEN TXEN
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:5
4
3
2
1
0
Name
reserved
DUPLEX
reserved
CRC
PADEN
TXEN
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0
Enable Duplex Mode
When set, this bit enables Duplex mode, allowing simultaneous
transmission and reception.
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0
Enable CRC Generation
When set this bit enables the automatic generation of the CRC and its
placement at the end of the packet. If this bit is clear, the frames placed
in the TX FIFO are sent exactly as they are written into the FIFO.
Note that this bit should generally be set.
R/W
0
Enable Packet Padding
When set, this bit enables the automatic padding of packets that do not
meet the minimum frame size.
Note that this bit should generally be set.
R/W
0
Enable Transmitter
When set, this bit enables the transmitter. When this bit is clear, the
transmitter is disabled.
July 16, 2014
519
Texas Instruments-Production Data