LM3S6611 Datasheet, PDF (566/647 Pages) List of Unclassifed Manufacturers – Microcontroller

Signal Tables
Table 17-1. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PA7
I/O
TTL
GPIO port A bit 7.
35
I2C1SDA
I/O
OD
I²C module 1 data.
36
VCCPHY
-
Power VCC of the Ethernet PHY.
37
RXIN
I
Analog RXIN of the Ethernet PHY.
38
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
39
GND
-
Power Ground reference for logic and I/O pins.
40
RXIP
I
Analog RXIP of the Ethernet PHY.
41
ERBIAS
I
Analog 12.4-kΩ resistor (1% precision) used internally for Ethernet PHY.
42
GNDPHY
-
Power GND of the Ethernet PHY.
43
TXOP
O
Analog TXOP of the Ethernet PHY.
44
VDD
-
Power Positive supply for I/O and some logic.
45
GND
-
Power Ground reference for logic and I/O pins.
46
TXON
O
Analog TXON of the Ethernet PHY.
47
PF0
I/O
TTL
GPIO port F bit 0.
48
OSC0
I
Analog Main oscillator crystal input or an external clock reference input.
49
OSC1
O
Analog Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
50
WAKE
I
TTL
An external input that brings the processor out of Hibernate mode
when asserted.
51
HIB
O
OD
An open-drain output with internal pull-up that indicates the
processor is in Hibernate mode.
XOSC0
52
I
Analog Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a crystal or a 32.768-kHz
oscillator for the Hibernation module RTC.
53
XOSC1
O
Analog Hibernation module oscillator crystal output. Leave unconnected
when using a single-ended clock source.
54
GND
-
Power Ground reference for logic and I/O pins.
VBAT
55
-
Power Power source for the Hibernation module. It is normally connected
to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
56
VDD
-
Power Positive supply for I/O and some logic.
57
GND
-
Power Ground reference for logic and I/O pins.
58
MDIO
I/O
TTL
MDIO of the Ethernet PHY.
PF3
I/O
TTL
GPIO port F bit 3.
59
LED0
O
TTL
Ethernet LED 0.
PF2
I/O
TTL
GPIO port F bit 2.
60
LED1
O
TTL
Ethernet LED 1.
61
PF1
I/O
TTL
GPIO port F bit 1.
62
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
63
GND
-
Power Ground reference for logic and I/O pins.
64
RST
I
TTL
System reset input.
65
CMOD0
I
TTL
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
566
July 16, 2014
Texas Instruments-Production Data