LM3S6611 Datasheet, PDF (166/647 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
5.2.1
5.2.2
5.2.2.1
5.2.2.2
■ Local control, such as reset (see “Reset Control” on page 166), power (see “Power
Control” on page 170) and clock control (see “Clock Control” on page 171)
■ System control (Run, Sleep, and Deep-Sleep modes); see “System Control” on page 176
Device Identification
Several read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers.
Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
CMOD0 and CMOD1 Test-Mode Control Pins
Two pins, CMOD0 and CMOD1, are defined for internal use for testing the microcontroller during
manufacture. They have no end-user function and should not be used. The CMOD pins should be
connected to ground.
Reset Sources
The controller has five sources of reset:
1. External reset input pin (RST) assertion; see “External RST Pin” on page 167.
2. Power-on reset (POR); see “Power-On Reset (POR)” on page 167.
3. Internal brown-out (BOR) detector; see “Brown-Out Reset (BOR)” on page 168.
4. Software-initiated reset (with the software reset registers); see “Software Reset” on page 169.
5. A watchdog timer reset condition violation; see “Watchdog Timer Reset” on page 169.
Table 5-3 provides a summary of results of the various reset operations.
Table 5-3. Reset Sources
Reset Source
Core Reset?
JTAG Reset?
On-Chip Peripherals Reset?
Power-On Reset
Yes
Yes
Yes
RST
Yes
Pin Config Only
Yes
Brown-Out Reset
Yes
No
Yes
Software System Request
Yes
No
Yes
Reset^a
Software Peripheral Reset
No
No
Yes^b
Watchdog Reset
Yes
No
Yes
a. By using the SYSRESREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control (APINT) register
b. Programmable on a module-by-module basis using the Software Reset Control Registers.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
or an external reset is the cause, and then all the other bits in the RESC register are cleared except
for the POR or EXT indicator.
166
July 16, 2014
Texas Instruments-Production Data