LM3S6611 Datasheet, PDF (25/647 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S6611 Microcontroller
Table 1. Revision History (continued)
Date
July 2009
Revision Description
5902 ■ Clarified Power-on reset and RST pin operation; added new diagrams.
■ Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL)
registers.
■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.
■ Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1
registers.
■ Added description for Ethernet PHY power-saving modes.
■ Corrected the reset values for bits 6 and 7 in the Ethernet MR24 register.
■ Changed buffer type for WAKE pin to TTL and HIB pin to OD.
■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added E_IR
(Internal voltage reference error) parameter.
■ Additional minor data sheet clarifications and corrections.
April 2009
5367
■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 159).
■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
of the output divisor.
■ Added "GPIO Module DC Characteristics" table (see Table 19-4 on page 594).
■ Additional minor data sheet clarifications and corrections.
January 2009
4660
■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.
■ Clarification added as to what happens when the SSI in slave mode is required to transmit but there
is no data in the TX FIFO.
■ Added "Hardware Configuration" section to Ethernet Controller chapter.
■ Additional minor data sheet clarifications and corrections.
November 2008
4283
■ Revised High-Level Block Diagram.
■ Additional minor data sheet clarifications and corrections were made.
October 2008
4149
■ Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG)
register.
■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the
Internal Memory chapter. The correct value is 0x0000.0006.
■ In the Ethernet chapter, major improvements were made including a rewrite of the conceptual
information and the addition of new figures to clarify how to use the Ethernet Controller interface.
■ Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter.
August 2008
3447
■ Added note on clearing interrupts to Interrupts chapter.
■ Added Power Architecture diagram to System Control chapter.
■ Additional minor data sheet clarifications and corrections.
July 16, 2014
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