LM3S6611 Datasheet, PDF (167/647 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S6611 Microcontroller
5.2.2.3
5.2.2.4
Power-On Reset (POR)
Note: The power-on reset also resets the JTAG controller. An external reset does not.
The internal Power-On Reset (POR) circuit monitors the power supply voltage (V_DD) and generates
a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a
threshold value (V_TH). The microcontroller must be operating within the specified operating parameters
when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the microcontroller
must reach 3.0 V within 10 msec of V_DD crossing 2.0 V to guarantee proper operation. For applications
that require the use of an external reset signal to hold the microcontroller in reset longer than the
internal POR, the RST input may be used as discussed in “External RST Pin” on page 167.
The Power-On Reset sequence is as follows:
1. The microcontroller waits for internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset
timing is shown in Figure 19-6 on page 601.
External RST Pin
Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be
sure to place any components connected to the RST signal as close to the microcontroller
as possible.
If the application only uses the internal POR circuit, the RST input must be connected to the power
supply (V_DD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 167.
Figure 5-1. Basic RST Configuration
VDD
Stellaris®
R_PU
RST
R_PU = 0 to 100 kΩ
The external reset pin (RST) resets the microcontroller including the core and all the on-chip
peripherals except the JTAG TAP controller (see “JTAG Interface” on page 152). The external reset
sequence is as follows:
1. The external reset pin (RST) is asserted for the duration specified by T_MIN and then de-asserted
(see “Reset” on page 600).
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
July 16, 2014
167
Texas Instruments-Production Data