LM3S6611 Datasheet, PDF (11/647 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S6611 Microcontroller
Figure 13-1. I²C Block Diagram ............................................................................................. 466
Figure 13-2. I²C Bus Configuration ........................................................................................ 467
Figure 13-3. START and STOP Conditions ............................................................................. 467
Figure 13-4. Complete Data Transfer with a 7-Bit Address ....................................................... 468
Figure 13-5. R/S Bit in First Byte ............................................................................................ 468
Figure 13-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 468
Figure 13-7. Master Single SEND .......................................................................................... 472
Figure 13-8. Master Single RECEIVE ..................................................................................... 473
Figure 13-9. Master Burst SEND ........................................................................................... 474
Figure 13-10. Master Burst RECEIVE ...................................................................................... 475
Figure 13-11. Master Burst RECEIVE after Burst SEND ............................................................ 476
Figure 13-12. Master Burst SEND after Burst RECEIVE ............................................................ 477
Figure 13-13. Slave Command Sequence ................................................................................ 478
Figure 14-1. Ethernet Controller ............................................................................................. 503
Figure 14-2. Ethernet Controller Block Diagram ...................................................................... 503
Figure 14-3. Ethernet Frame ................................................................................................. 505
Figure 14-4. Interface to an Ethernet Jack .............................................................................. 511
Figure 15-1. Analog Comparator Module Block Diagram ......................................................... 550
Figure 15-2. Structure of Comparator Unit .............................................................................. 552
Figure 15-3. Comparator Internal Reference Structure ............................................................ 552
Figure 16-1. 100-Pin LQFP Package Pin Diagram .................................................................. 562
Figure 16-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 563
Figure 19-1. Load Conditions ................................................................................................ 597
Figure 19-2. JTAG Test Clock Input Timing ............................................................................. 599
Figure 19-3. JTAG Test Access Port (TAP) Timing .................................................................. 599
Figure 19-4. JTAG TRST Timing ............................................................................................ 600
Figure 19-5. External Reset Timing (RST) .............................................................................. 600
Figure 19-6. Power-On Reset Timing ..................................................................................... 601
Figure 19-7. Brown-Out Reset Timing .................................................................................... 601
Figure 19-8. Software Reset Timing ....................................................................................... 601
Figure 19-9. Watchdog Reset Timing ..................................................................................... 601
Figure 19-10. Hibernation Module Timing ................................................................................. 602
Figure 19-11. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 603
Figure 19-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 604
Figure 19-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 604
Figure 19-14. I²C Timing ......................................................................................................... 605
Figure 19-15. External XTLP Oscillator Characteristics ............................................................. 607
Figure D-1. Stellaris LM3S6611 100-Pin LQFP Package Dimensions ...................................... 635
Figure D-2. 100-Pin LQFP Tray Dimensions .......................................................................... 637
Figure D-3. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 638
Figure D-4. Stellaris LM3S6611 108-Ball BGA Package Dimensions ....................................... 639
Figure D-5. 108-Ball BGA Tray Dimensions ........................................................................... 641
Figure D-6. 108-Ball BGA Tape and Reel Dimensions ............................................................ 642
July 16, 2014
11
Texas Instruments-Production Data