LM3S6611 Datasheet, PDF (508/647 Pages) List of Unclassifed Manufacturers – Microcontroller

Ethernet Controller
14.3.1.4
Ethernet Reception Options
The Ethernet Controller RX FIFO should be cleared during software initialization. The receiver should
first be disabled by clearing the RXEN bit in the Ethernet MAC Receive Control (MACRCTL)
register, then the FIFO can be cleared by setting the RSTFIFO bit in the MACRCTL register.
The receiver automatically rejects frames that contain bad CRC values in the FCS field. In this case,
a Receive Error interrupt is generated and the receive data is lost. To accept all frames, clear the
BADCRC bit in the MACRCTL register.
In normal operating mode, the receiver accepts only those frames that have a destination address
that matches the address programmed into the Ethernet MAC Individual Address 0 (MACIA0)
and Ethernet MAC Individual Address 1 (MACIA1) registers. However, the Ethernet receiver can
also be configured for Promiscuous and Multicast modes by setting the PRMS and AMUL bits in the
MACRCTL register.
14.3.2
Internal MII Operation
For the MII management interface to function properly, the MDIO signal must be connected through
a 10k Ω pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor prevents
management transactions on this internal MII to function. Note that it is possible for data transmission
across the MII to still function since the PHY layer auto-negotiates the link parameters by default.
For the MII management interface to function properly, the internal clock must be divided down from
the system clock to a frequency no greater than 2.5 MHz. The Ethernet MAC Management Divider
(MACMDV) register contains the divider used for scaling down the system clock. See page 527 for
more details about the use of this register.
14.3.3
PHY Operation
The Physical Layer (PHY) in the Ethernet Controller includes integrated ENDECs,
scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions.
The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an
adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery.
The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX
applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The
Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external
filter is required.
14.3.3.1
Clock Selection
The Ethernet Controller has an on-chip crystal oscillator which can also be driven by an external
oscillator. In this mode of operation, a 25-MHz crystal should be connected between the XTALPPHY
and XTALNPHY pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY
pin. In this mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground.
14.3.3.2
Auto-Negotiation
The Ethernet Controller supports the auto-negotiation functions of Clause 28 of the IEEE 802.3
standard for 10/100 Mbps operation over copper wiring. This function is controlled via register
settings. The auto-negotiation function is turned on by default, and the ANEGEN bit in the Ethernet
PHY Management Register 0 - Control (MR0) is set after reset. Software can disable the
auto-negotiation function by clearing the ANEGEN bit. The contents of the Ethernet PHY Management
Register - Auto-Negotiation Advertisement (MR4) are reflected to the Ethernet Controller’s link
partner during auto-negotiation via fast-link pulse coding.
508
July 16, 2014
Texas Instruments-Production Data