LM3S6611 Datasheet, PDF (19/647 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S6611 Microcontroller
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Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 366
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 367
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 368
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 369
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 370
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 371
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 372
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 373
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 374
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 375
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 376
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 377
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 378
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 379
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 380
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 381
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 382
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 383
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 384
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 394
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 396
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 398
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 400
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 401
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 402
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 403
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 405
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 407
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 409
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 411
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 412
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 413
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 415
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 416
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 417
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 418
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 419
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 420
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 421
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 422
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 423
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 424
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 425
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 426
Synchronous Serial Interface (SSI) ............................................................................................ 427
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 440
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 442
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 444
July 16, 2014
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