LM3S6611 Datasheet, PDF (10/647 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
List of Figures
Figure 1-1. Stellaris LM3S6611 Microcontroller High-Level Block Diagram ............................... 39
Figure 2-1. CPU Block Diagram ............................................................................................. 48
Figure 2-2. TPIU Block Diagram ............................................................................................ 49
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 51
Figure 2-4. Bit-Band Mapping ................................................................................................ 71
Figure 2-5. Data Storage ....................................................................................................... 72
Figure 2-6. Vector Table ........................................................................................................ 78
Figure 2-7. Exception Stack Frame ........................................................................................ 80
Figure 3-1. SRD Use Example ............................................................................................... 94
Figure 4-1. JTAG Module Block Diagram .............................................................................. 153
Figure 4-2. Test Access Port State Machine ......................................................................... 157
Figure 4-3. IDCODE Register Format ................................................................................... 163
Figure 4-4. BYPASS Register Format ................................................................................... 163
Figure 4-5. Boundary Scan Register Format ......................................................................... 164
Figure 5-1. Basic RST Configuration .................................................................................... 167
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 168
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 168
Figure 5-4. Power Architecture ............................................................................................ 171
Figure 5-5. Main Clock Tree ................................................................................................ 173
Figure 6-1. Hibernation Module Block Diagram ..................................................................... 230
Figure 6-2. Clock Source Using Crystal ................................................................................ 232
Figure 6-3. Clock Source Using Dedicated Oscillator ............................................................. 233
Figure 7-1. Flash Block Diagram .......................................................................................... 250
Figure 8-1. GPIO Port Block Diagram ................................................................................... 283
Figure 8-2. GPIODATA Write Example ................................................................................. 284
Figure 8-3. GPIODATA Read Example ................................................................................. 284
Figure 9-1. GPTM Module Block Diagram ............................................................................ 325
Figure 9-2. 16-Bit Input Edge Count Mode Example .............................................................. 329
Figure 9-3. 16-Bit Input Edge Time Mode Example ............................................................... 330
Figure 9-4. 16-Bit PWM Mode Example ................................................................................ 331
Figure 10-1. WDT Module Block Diagram .............................................................................. 361
Figure 11-1. UART Module Block Diagram ............................................................................. 385
Figure 11-2. UART Character Frame ..................................................................................... 387
Figure 11-3. IrDA Data Modulation ......................................................................................... 389
Figure 12-1. SSI Module Block Diagram ................................................................................. 427
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 430
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 431
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 432
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 432
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 433
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 434
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 434
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 435
Figure 12-10. MICROWIRE Frame Format (Single Frame) ........................................................ 436
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 437
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 437
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July 16, 2014
Texas Instruments-Production Data