SMJ626162 Datasheet, PDF (9/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
setting the mode register
The ’626162 contains a mode register that must be programmed with the read latency, the burst type, and the
burst length. This is accomplished by executing a mode-register set (MRS) command with the information
entered on address lines A0–A9. A logic 0 must be entered on A7 and A8. A10 and A11 are don’t care entries
for the ’626162. When A9 = 1, the write-burst length is always 1. When A9 = 0, the write-burst length is defined
by A0–A2. Figure 1 shows the valid combinations for a successful MRS command. Only valid addresses allow
the mode register to be changed. If the addresses are not valid, the previous contents of the mode register
remain unaffected. The MRS command is executed by holding RAS, CAS, and W low and the input-mode word
valid on A0–A9 on the rising edge of CLK (see Table 1). The MRS command can be executed only when both
banks are deactivated.
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Reserved
0
0
0 = Serial
1 = Interleave
(burst type)
REGISTER
BIT A9
WRITE-
BURST
LENGTH
REGISTER
BITS†
A6 A5 A4
READ
LATENCY‡
REGISTER
BITS†
A2 A1 A0
0
A2–A0
1
1
010
2
011
3
000
001
010
011
111
† _{All other combinations are reserved.}
‡ _{See the timing requirements for minimum valid read latencies based on maximum frequency rating.}
BURST LENGTH
1
2
4
8
256
refresh
Figure 1. Mode-Register Programming
The ’626162 must be refreshed at intervals not exceeding t_REF (see timing requirements) or data cannot be
retained. Refresh can be accomplished by performing a read or write access to every row in both banks, or by
performing 4096 autorefresh (REFR) commands. Regardless of the method used, refresh must be
accomplished before t_REF has expired.
autorefresh (REFR)
Before performing a REFR operation, both banks must be deactivated (placed in precharge). To enter a REFR
command, RAS and CAS must be low and W must be high upon the rising edge of CLK (see Table 1). The
refresh address is generated internally such that after 4096 REFR commands, both banks of the ’626162 have
been refreshed. The external address and bank select (A11) are ignored. The execution of a REFR command
automatically deactivates both banks upon completion of the internal autorefresh cycle. This allows consecutive
REFR-only commands to be executed, if desired, without any intervening DEAC commands. The REFR
commands do not necessarily have to be consecutive, but all 4096 must be completed before t_REF expires.
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