SMJ626162 Datasheet, PDF (12/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
interrupted bursts (continued)
CLK
nCCD = 1 Cycle
WRT
Command
READ
Command
DQ
D
Q
Q
Q
NOTE A: For this example, assume read latency = 3 and burst length = 4.
Figure 5. Write Burst Interrupted by Read Command
nCCD = 2 Cycles
CLK
WRT Command
at Column
Address C0
DQ
C0
Interrupting
WRT Command
at Column Address C1
C0 + 1
C1
C1 + 1
C1 + 2
C1 + 3
NOTE A: For this example, assume burst length = 4.
Figure 6. Write Burst Interrupted by Write Command
CLK
DQ
DQMx
nCCD = 3 Cycles
WRT Command
D
D
Interrupting
DEAC or DCAB
Command
Ignored
Ignored
tRWL
NOTE A: For this example, assume burst length = 4.
Figure 7. Write Burst Interrupted by DEAC/DCAB Command
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