SMJ626162 Datasheet, PDF (5/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

operation (continued)
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
Table 3. Data Mask (DQM) Command Truth Table^†
COMMAND
STATE OF
BANK(S)
DQML
DQMU‡
(n)
DATA IN
(n)
DATA OUT
(n + 2)
MNEMONIC
T = deac
—
and
X
N/A
Hi-Z
—
B = deac
T = actv
—
and
B = actv
X
N/A
Hi-Z
—
( no access operation )§
Data-in enable
T = write
or
B = write
L
V
N/A
ENBL
Data-in mask
T = write
or
B = write
H
M
N/A
MASK
Data-out enable
T = read
or
B = read
L
N/A
V
ENBL
T = read
Data-out mask
or
H
N/A
Hi-Z
MASK
B = read
† _{For execution of these commands on cycle n, one of the following must be true:}
– CKE (n) must be high
– tCESP must be satisfied for power-down exit
– tCES and nCLE must be satisfied for clock-suspend exit.
CS(n), RAS(n), CAS(n), W(n), and A0 – A11 are irrelevant.
‡ _{DQML controls DQ0 – DQ7.}
DQMU controls DQ8 – DQ15.
§ _{A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation and two cycles after the last data-in cycle}
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.
Legend:
n = CLK cycle number
L = Logic low
H = Logic high
X = Don’t care, either logic low or logic high
V = Valid
M = Masked input data
N/A = Not applicable
T = Bank T
B = Bank B
actv = Activated
deac = Deactivated
write = Activated and accepting data in on cycle n
read = Activated and delivering data out on cycle (n + 2)
Hi-Z = High-impedance state
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