SMJ626162 Datasheet, PDF (32/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

CLK
DQ
DQMx
RAS
CAS
W
A10
A11
A0 – A9
CS
CKE
ACTV B
READ B
R0
R0
C0
ACTV T
DEAC B
WRT T
a
b
c
d
e
f
g
h
DEAC T
R1
R1
C1
BURST
TYPE
BANK
ROW
BURST CYCLE†
(D/Q) (B/ T ) ADDR
a
b
c
d
e
f
g
h
Q
B
R0
C0 C0 + 1 C0 + 2 C0 + 3
D
T
R1
C1 C1 + 1 C1 + 2 C1 + 3
† _{Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5.)}
NOTE A: This example illustrates minimum tRCD, nEP, and tRWL for the ’626162-15 at 66 MHz.
Figure 27. Read-Burst Bank B, Write-Burst Bank T (read latency = 3, burst length = 4)