SMJ626162 Datasheet, PDF (37/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

CLK
DQ0 – DQ7
DQML
DQ8 – DQ15
DQMU
RAS
CAS
W
A10
A11
A0 – A9
CS
CKE
ACTV T
READ T
R0
R0
C0
ACTV B
a
b
c
d
WRT B
f
DCAB
h
a
b
c
d
e
f
g
h
R1
R1
C1
BURST
TYPE
BANK
ROW
BURST CYCLE†
(D/Q) (B/ T ) ADDR
a
b
c
d
e
f
g
h
Q
T
R0
C0 C0 + 1 C0 + 2 C0 + 3
D
B
R1
C1 C1 + 1 C1 + 2 C1 + 3
† _{Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).}
NOTE A: This example illustrates minimum tRCD and tRWL for the ’626162-15 at 66 MHz.
Figure 32. Data Mask With Cycle-by-Cycle Byte Control (read latency = 3, burst length = 4)