SMJ626162 Datasheet, PDF (29/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

CLK
DQ0
DQMx
RAS
CAS
W
A10
A11
A0 – A9
CS
CKE
ACTV B READ- P B
R0
R0
C0
n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14
n+253 n+254 n+255
BURST
TYPE
BANK
ROW
BURST CYCLE†
(D/Q) (B/ T ) ADDR a b c d e
f
gh
i
j
k
l
mn
o
p
q
r
s ..
Q
B
R0
C0 C0 + 1 C0 + 2 C0 + 3 C0 + 4 C0 + 5 C0 + 6 C0 + 7
255
† _{Column-address sequence depends on programmed burst type and starting column address C0.}
NOTE A: This example illustrates minimum tRCD for the ’626162-15 at 66 MHz.
Figure 24. Read Burst – Full Page (read latency = 3, burst length = 256)