SMJ626162 Datasheet, PDF (4/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
operation (continued)
Table 2. Clock-Enable (CKE) Command Truth Table^†
COMMAND
CKE CKE CS RAS CAS
W
STATE OF BANK(S)
(n – 1)
(n)
(n)
(n)
(n)
(n) ^MNEMONIC
Power-down entry on cycle (n + 1)‡
T = no access operation§
B = no access operation§
H
L
X
X
X
X
PDE
Power-down exit¶
T = power down
B = power down
L
H
X
X
X
X
—
CLK suspend on cycle (n + 1)
T = access operation§
B = access operation§
H
L
X
X
X
X
HOLD
CLK suspend exit on cycle (n + 1)
T = access operation§
B = access operation§
L
H
X
X
X
X
—
† _{For execution of these commands, A0 – A11 (n) and DQMx (n) are don’t care entries.}
‡ _{On cycle n, the device executes the respective command (listed in Table 1). On cycle (n + 1), the device enters power-down mode.}
§ _{A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation and two cycles after the last data-in cycle}
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.
¶ _{If setup time from CKE high to the next CLK high satisfies tCESP , the device executes the respective command (listed in Table 1). Otherwise,}
either a DESL or a NOOP command must be applied before any other command.
Legend:
n = CLK cycle number
L = Logic low
H = Logic high
X = Don’t care, either logic low or logic high
T = Bank T
B = Bank B
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