SMJ626162 Datasheet, PDF (30/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

CLK
DQ
DQMx
RAS
CAS
W
A10
A11
A0 – A9
CS
CKE
ACTV B READ- P B
R0
R0
C0
ACTV T READ- P T
ACTV B READ- P B
ACTV T
abc
de
f
gh
i
j
k
l mn o p q
r
s
R1
R1
C1
R2
R3
R2
C2
R3
BURST
TYPE
BANK
ROW
BURST CYCLE†
(D/Q) (B/ T ) ADDR a b c d e
f
gh
i
j
k
l
mn
o
p
q
r
s ..
Q
B
R0
C0 C0 + 1 C0 + 2 C0 + 3 C0 + 4 C0 + 5 C0 + 6 C0 + 7
Q
T
R1
C1 C1 + 1 C1 + 2 C1 + 3 C1 + 4 C1 + 5 C1 + 6 C1 + 7
Q
B
R2
C2 C2 + 1 C2 + 2 . .
† _{Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 6).}
NOTE A: This example illustrates minimum tRCD for the ’626162-15 at 66 MHz.
Figure 25. Two-Bank Row-Interleaving Read Bursts With Automatic Deactivate (read latency = 3, burst length = 8)