SMJ626162 Datasheet, PDF (16/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 7)
PARAMETER
MIN MAX UNIT
Ci(S) Input capacitance, CLK input
8 pF
Ci(AC) Input capacitance, address and control inputs: A0–A11, CS, DQMx, RAS, CAS, W
8 pF
Ci(E) Input capacitance, CKE input
8 pF
Co
Output capacitance
10 pF
NOTE 7: Capacitance is sampled only at initial design and after any major changes. Samples are tested at 0 V and 25°C with a 1-MHz signal
applied to the pin under test. All other pins are open.
ac timing requirements^†‡
’626162-12
MIN MAX
’626162-15
MIN MAX
’626162-20
UNIT
MIN MAX
Read latency = 2
15
20
30
tCK Cycle time, CLK (system clock)
Read latency = 3
12
15
ns
20
tCKH Pulse duration, CLK (system clock) high
4
tCKL Pulse duration, CLK (system clock) low
4
tAC
Access time, CLK ↑ to data out
(see Note 8)
Read latency = 2
Read latency = 3
4
4
9
8
4
4
15
9
ns
ns
20
ns
10
tLZ
Delay time, CLK to DQ in the low-impedance state (see Note 9)
0
tHZ
Delay time, CLK to DQ in the
high-impedance state (see Note 10)
Read latency = 2
Read latency = 3
0
8
8
0
14
11
ns
15
ns
12
tDS Setup time, data input
3
4
4
ns
tAS
Setup time, address
3
4
4
ns
tCS Setup time, control input (CS, RAS, CAS, W, DQMx)
3
4
4
ns
tCES Setup time, CKE (suspend entry/exit, power-down entry)
3
4
4
ns
tCESP Setup time, CKE (power-down/self-refresh exit) (see Note 11)
10
10
10
ns
tOH Hold time, CLK ↑ to data out
1.5
2
2
ns
tDH Hold time, data input
2
2
2
ns
tAH Hold time, address
2
2
2
ns
tCH Hold time, control input (CS, RAS, CAS, W, DQMx)
2
2
2
ns
tCEH Hold time, CKE
2
2
2
ns
tRC
REFR command to ACTV, MRS, or REFR command;
ACTV command to ACTV, MRS, or REFR command
96
120
160
ns
tRAS ACTV command to DEAC or DCAB command
60 100 000
75 100 000 100 100 000 ns
tRCD ACTV command to READ or WRT command (see Note 12)
24
30
40
ns
tRP DEAC or DCAB command to ACTV, MRS, or REFR command
36
45
60
ns
† _{See Parameter Measurement Information for load circuits.}
‡ _{All references are made to the rising transition of CLK unless otherwise noted.}
NOTES: 8. tAC is referenced from the rising transition of CLK that precedes the data-out cycle. For example, the first data-out tAC is referenced
from the rising transition of CLK that is one cycle before read latency for the READ command. Access time is measured at output
reference level 1.4 V.
9. tLZ is measured from the rising transition of CLK that is one cycle before read latency for the READ command.
10. tHZ (MAX) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.
11. See Figure 18.
12. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
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