SMJ626162 Datasheet, PDF (11/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

interrupted bursts (continued)
SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
CLK
READ Command
nCCD = 5 Cycles
Interrupting
WRT Command
DQ
Q
D
D
DQMx
See Note B
NOTES: A. For this example, assume read latency = 3 and burst length = 4.
B. DQMx must be high to mask output of the read burst on cycles (nCCD – 1), nCCD, and (nCDD + 1).
Figure 3. Read Burst Interrupted by Write Command
nCCD = 2 Cycles
CLK
READ Command
Interrupting
DEAC/DCAB
Command
nHZP
DQ
Q
Q
NOTE A: For this example, assume read latency = 3 and burst length = 4.
Figure 4. Read Burst Interrupted by DEAC Command
INTERRUPTING
COMMAND
READ, READ-P
WRT, WRT-P
DEAC, DCAB
Table 8. Write-Burst Interruption
EFFECT OR NOTE ON USE DURING WRITE BURST
Data that was input on the previous cycle is written; no further data inputs are accepted (see Figure 5).
The new WRT (WRT-P) command and data inputs immediately supersede the write burst in progress
(see Figure 6).
The DEAC/DCAB command immediately supersedes the write burst in progress. DQMx must be used to
mask the DQ bus such that the write recovery specification (tRWL) is not violated by the
interrupt (see Figure 7).
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