SMJ626162 Datasheet, PDF (1/42 Pages) Texas Instruments – 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY

SMJ626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SGMS737C – JULY 1997 – REVISED MARCH 1999
D Organization
512K × 16 Bits × 2 Banks
D 3.3-V Power Supply (±5% Tolerance)
D Two Banks for On-Chip Interleaving
(Gapless Accesses)
D High Bandwidth – Up to 83-MHz Data Rates
D Read Latency Programmable to
2 or 3 Cycles From Column-Address Entry
D Burst Sequence Programmable to Serial or
Interleave
D Burst Length Programmable to 1, 2, 4, 8, or
256 (Full Page)
D Chip Select and Clock Enable for Enhanced
System Interfacing
D Cycle-by-Cycle DQ-Bus Mask Capability
With Upper- and Lower-Byte Control
D Autorefresh Capability
D 4K Refresh (Total for Both Banks)
D High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
D Power-Down Mode
D Pipeline Architecture
D Temperature Ranges:
Operating, – 55°C to 125°C
Storage, – 65°C to 150°C
D Performance Ranges:
SYNCHRONOUS ACCESS TIME REFRESH
CLOCK CYCLE
CLOCK TO
TIME
TIME
OUTPUT
INTERVAL
’626162-12
’626162-15
’626162-20
† _{Read latency = 3}
tCK
(MIN)^{
12 ns
15 ns
20 ns
tAC
(MIN)^{
8 ns
9 ns
10 ns
tREF
(MAX)
32 ms
32 ms
32 ms
description
The SMJ626162 series of devices are
16 777 216-bit synchronous dynamic random-
access memory (SDRAM) devices organized as
two banks of 524 288 words with 16 bits per word.
All inputs and outputs of the SMJ626162 series
are compatible with the LVTTL interface.
HKD PACKAGE
(TOP VIEW)
V_CC 1
DQ0 2
DQ1 3
V_SSQ 4
DQ2 5
DQ3 6
V_CCQ 7
DQ4 8
DQ5 9
V_SSQ 10
DQ6 11
DQ7 12
V_CCQ 13
DQML 14
W 15
CAS 16
RAS 17
CS 18
A11 19
A10 20
A0 21
A1 22
A2 23
A3 24
V_CC 25
50 V_SS
49 DQ15
48 DQ14
47 V_SSQ
46 DQ13
45 DQ12
44 V_CCQ
43 DQ11
42 DQ10
41 V_SSQ
40 DQ9
39 DQ8
38 V_CCQ
37 NC
36 DQMU
35 CLK
34 CKE
33 NC
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 V_SS
A[0:10]
A11
CAS
CKE
CLK
CS
DQ[0:15]
DQML, DQMU
NC
RAS
VCC
VCCQ
VSS
VSSQ
W
PIN NOMENCLATURE
Address Inputs
A0–A10 Row Addresses
A0–A7 Column Addresses
A10 Automatic-Precharge Select
Bank Select
Column-Address Strobe
Clock Enable
System Clock
Chip Select
SDRAM Data Input/Data Output
Data-Input/Data-Output Mask Enable
No Connect
Row-Address Strobe
Power Supply (3.3-V Typical)
Power Supply for Output Drivers
(3.3-V Typical)
Ground
Ground for Output Drivers
Write Enable
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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